Electrical Integrity


The interconnects operating at high frequency and fast switching rates demand SI analysis for right design at first time. Caliber Interconnect's SI engineers are having strong knowledge in SI theory and expertise in simulation tools to analyze various SI issues like reflection due to impedance mismatch, crosstalk, signal attenuation and PDN noise which affects the interconnect performance. The SI analysis is carried out in two phase, the pre and post layout analysis.

Pre-layout analysis: Planning the stack-up for controlled impedance, dielectric material selection for high frequency operation, I/O buffer selection from different derive strength, topology optimization, termination strategy, routing specifications (Trace width, spacing and length matching) and floor planning for critical components are various sections in pre-layout analysis.

Post layout analysis: Simulation of routed board for potential SI issues like reflection, overshoot/undershoot, crosstalk, attenuation and EMI issues. The post layout report is prepared from simulation results along with suggestions for topology modification, termination schemes and layout modification to achieve good signal integrity for any SI issues.

For Printed Circuit Boards
Signal Integrity Analysis
  • Reflection, Ringing and Overshoot/Undershoot
  • Single ended and Differential Crosstalk Analysis
  • Signal Attenuation due to IR-Drop, Skin-effect and Dielectric Loss
  • Channel Analysis for Serial Communication – Eye Diagram Analysis
Timing Analysis
  • Common clocking(PCI, FSB)
  • Source synchronous clocking(DDR)
Power Integrity Analysis
  • SSN Analysis
  • IR- Drop Analysis
  • Power Distribution Network Impedance profile Analysis
  • De-coupling Capacitors Estimation and Placement Optimization
EMI/EMC Analysis
  • Net-wise radiated EMI Analysis
  • EMC Analysis based on FCC, CISPR and VCCI Requirements
S-parameter Analysis
  • Return loss, Insertion Loss, NEXT and FEXT study
    • Mixed mode Analysis for differential channel: Differential mode
  • Commom mode
  • Mode conversion EMI Radiation Susceptibility
Experience in various Interfacing Technologies
  • Parallel Technologies
    PCI, PCI-X
    SDRAM, QDR, DDR, DDR2 3
    FSB, Hub Interface
  • Serial Technologies
    USB, PCIe, HT, SATA
    SERDES, XAUI, RocketIO, Aurora, Gigabit Ethernet
    sRIO, CPRIO
Signal and Power Integrity Analysis
  • Reflection and Ringing Analysis
  • Single and Differential Crosstalk Analysis
  • Net-wise Radiated EMI Analysis
  • SSN Analysis
  • IR-Drop Analysis
  • Core Supply Noise Analysis
  • De-coupling Capacitors Estimation and Placement Optimization
Electrical Modeling
  • Parasitic RLGC Extraction
  • S-parameter Model
Analysis Tools Expertise
  • Cadence Allegro PCB SI/PI
  • Cadence Allegro Package SI/PI along with Paksi 3D
  • Cadence Allegro SiP SI/PI along with Paksi 3D
  • Cadence Allegro SigXplorer
  • Mentor Graphics Hyperlynx
  • LTSpice
Services