Services
SiP (System-in-Package)


Interconnection technology is now a powerful tool to design and produce functions which cannot be readily integrated on one silicon die for compatibility and cost reasons. The system in package(SIP) design solutions from Caliber Interconnect enables to shrink the size and weight of a Printed Wiring Board into a SIP with increased electrical performance .Also SIP technology provides alternative to challenges involved in integrating analog and digital functions into a SOC (System On Chip).The result is single package that combines all of the electronic components (Digital ICs, Analog ICs, RF ICs, passive components or other elements) needed to provide a system or sub-system. We offer semiconductor packaging solutions of high performance with reliability, Through our extensive experience with different manufacturers.

Applications
  • Cellular
  • Bluetooth
  • 802.11 WLAN
  • GPS
  • Camera
  • PDA
  • CMOS Sensors
SiP Advantage
  • Miniaturization due to fewer packages and 3D stacked die
  • Multiple technologies in a SiP
  • Reduced time-to-new product concepts
  • Faster design cycles (over SoC)
  • Reduce system board complexity and layer count
  • Performance through interconnect elimination
  • Low power and good Signal Integrity for High Speed Operation
  • Optimization of complexity, cost, and time to market
SiP Design Challenges
Signal integrity for high density interconnect
  • Cross talk
  • Impedance discontinuities (reflections)
  • Timing skew
  • Parasitic capacitance, resistance and inductance in long traces
Power integrity
  • Voltage drop for high speed signals (lead and trace inductance limits power delivery)
  • Ground noise due to high frequency current variations
Shielding
  • Radiated noise within the package at high frequency
  • External electromagnetic noise sources
Categories of SiP
SiP Design Inputs
  • Schematic or netlist for the SiP design and Bill of Material (BOM)
  • Diepad co-ordinates
  • The physical dimension details of the Die and footprints for the components
  • Signal Descriptions and Electrical constraints
  • The SiP physical dimension, BGA pin and layer details, if any
  • Impedance requirements and Layout Guidelines, if any
  • The DFM and DFA guidelines for the SiP
SiP Signal Integrity Analysis

The emergence of Systems in a Package introduces number of new challenges for testing . Before the prototype phase ,the SIPs has to undergo electrical analysis to identify potential signal and power integrity issues using accurate spice or IBIS models or extracting by simulation methodologies or realtime measurements. Our team is constantly investigating on viable simulation and measurement strategies for resolving signal and power integrity issues.

Pre-layout analysis

Determining optimal stack-up for controlled impedance, floor planning for critical components, critical nets IO buffer selection, topology optimization, termination strategy and routing specifications.

Post layout analysis

Verification and analysis of routed board for potential SI issues like reflection, overshoot/undershoot, crosstalk and EMI issues along with suggestions for topology modification, termination schemes and layout modification for good signal integrity.

Signal Integrity Analysis
  • Reflection, Ringing, Overshoot/Undershoot and Multiple Threshold Crossing
  • Single ended and Differential Crosstalk
  • Signal Attenuation Analysis for Skin-effect and Dielectric Loss
  • MGH Channel Analysis for Serial I/O – Eye Diagram and Bathtub curve Analysis
  • Timing Analysis
Power Integrity Analysis
  • SSN Analysis
  • Power Distribution Network Impedance Profile Analysis
  • IR-Drop Analysis
  • De-coupling Capacitors Estimation and Placement Optimization
EMI/EMC Analysis
  • Radiated EMI Analysis and Rectification
  • EMC Analysis based on FCC, CISPR and VCCI Requirements
Electrical Modelling
  • Parasitic RLC Extraction
  • Package IBIS Model
  • SPICE Sub-circuit Model
  • S-parameter Model
S-parameter Analysis
  • Return Loss, Insertion Loss, NEXT and FEXT Analysis
  • Mixed-mode Analysis to study Common to Differential mode conversion and EMI Radiation & Susceptibility
SiP Design EDA Tool Expertise
  • Cadence SiP Digital
  • Cadence SiP RF